// Example netlist for an inverter simulation

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// Sources
// NB - You should consider including a separate file that 
//   contains the source definitions for complicated circuits
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// NB - pvdd is a parameter that we will define in the .ocn file
//      you may define it here by uncommenting the following line:
//parameters pvdd=1.0v
VVDD ( VDD 0 ) vsource dc=pvdd
VVSS ( VSS 0 ) vsource dc=0
//VVIN1 ( A 0 ) vsource type=pulse val0=0 val1=pvdd delay=0 rise=0.01n fall=0.01n width=1n period=2n
//VVIN2 ( B 0 ) vsource type=pulse val0=0 val1=pvdd delay=0 rise=0.01n fall=0.01n width=2n period=4n
VCLK ( clock 0) vsource type=pulse val0=0 val1=pvdd delay=0 rise=0.01n fall=0.01n width=0.25n period=0.5n
VCLKB ( clockb 0) vsource type=pulse val0=pvdd val1=0 delay=0 rise=0.01n fall=0.01n width=0.25n period=0.5n
VVIN1 ( A 0 ) vsource dc=0
VVIN3 ( B 0 ) vsource dc=0
VVIN5 ( C 0 ) vsource dc=0


VVIN6 ( D 0 ) vsource dc=1
VVIN2 (ANOT 0 ) vsource dc=0
VVIN4 ( BNOT 0 ) vsource dc=1


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// Netlist: an inverter
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subckt inv out in vdd! gnd
XP ( out in vdd! vdd! ) PFET w=wdef l=ldef
XN ( out in gnd gnd ) NFET w=wdef l=ldef
ends inv
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// Netlist: a NAND gate
///////////////////////////////////////////////////////
subckt nand out inA inB inC vdd! gnd
P0 ( out inA vdd! vdd!) PFET w=(3/4)*wdef l=ldef
P1 ( out inB vdd! vdd!) PFET w=(3/4)*wdef l=ldef
P2 ( out inC vdd! vdd!) PFET w=(3/4)*wdef l=ldef
N0 ( out inA net1 gnd) NFET w=(3/4)*wdef l=ldef
N1 ( net1 inB net2 gnd) NFET w=(3/4)*wdef l=ldef
N2 ( net2 inC gnd gnd) NFET w=(3/4)*wdef l=ldef
ends nand
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// Netlist: a clocked inverter
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subckt clkinv out in nclk pclk vdd! gnd
M0 (net1 in vdd! vdd!) PFET w=wdef l=ldef
M1 (out pclk net1 vdd!) PFET w=wdef l=ldef
M2 (out nclk net2 gnd) NFET w=wdef l=ldef
M3 (net2 in gnd gnd) NFET w=wdef l=ldef
ends clkinv
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// Netlist: a D flip-flop
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subckt reg q d clk clkbar vdd! gnd
SE1 (out1 d clkbar clk vdd! gnd) clkinv
latch1inv (out1b out1 vdd! gnd) inv
SE2 (out1 out1b clk clkbar vdd! gnd) clkinv
SE3 (q out1 clk clkbar vdd! gnd) clkinv
latch2inv (out2b q vdd! gnd) inv
SE4 (q out2b clkbar clk vdd! gnd) clkinv
ends reg
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// Netlist: buffer
///////////////////////////////////////////////////
subckt buff out in vdd! gnd
INV1 (net2 in vdd! gnd) inv
INV2 (out net2 vdd! gnd) inv
ends buff

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// Netlist: XOR
//////////////////////////////////////////////////
subckt xor out a anot b bnot vdd! gnd
N10 (out anot net11 gnd) NFET w=wdef l=ldef
N11 (out b net11 gnd) NFET w=wdef l=ldef
N12 (net11 a gnd gnd) NFET w=wdef l=ldef
N13 (net11 bnot gnd gnd) NFET w=wdef l=ldef
P10 (out b net13 vdd!) PFET w=wdef l=ldef
P11 (out bnot net14 vdd!) PFET w=wdef l=ldef
P12 (net13 anot vdd! vdd!) PFET w=wdef l=ldef
P13 (net14 a vdd! vdd!) PFET w=wdef l=ldef
ends xor
/////////////////////////////////////////////////

// Test circuit
buffA (abuff A VDD VSS) buff
buffB (bbuff B VDD VSS) buff
buffANOT (anotbuff ANOT VDD VSS) buff
buffBNOT (bnotbuff BNOT VDD VSS) buff
buffC (cbuff C VDD VSS) buff
buffclk (clkbuff clock VDD VSS) buff
buffclkb (clkbbuff clockb VDD VSS) buff


NAND1 (y1 abuff bbuff cbuff VDD VSS) nand
//XOR1 (Y1 abuff anotbuff bbuff bnotbuff VDD VSS) xor
//NAND1 (Y1 abuff bbuff cbuff VDD VSS) nand 
//NAND2 (Y2 Y1 Y1 VDD VSS) nand
//REGISTER (Q Y2 clkbuff clkbbuff VDD VSS) reg 
